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high voltage latch - up proof, triple/quad spd t switches adg5433/adg5434 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.311 3 ? 2010 analog devices, inc. all rights reserved. features latch - up proof h uman body model (h bm ) esd rating : 8 kv low on resistance (13.5 ?) 9 v to 22 v dual - supply operation 9 v to 4 0 v single - supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd ana log signal range applications relay replacement automatic test equipment d ata acquisition instrumentation avionics audio and video switching communication systems functional block dia grams in1 in2 in3 en s1a d1 s1b s2b d2 s2a s3b d3 s3a logic adg5433 switches shown for a logic 1 input. 09207-001 figure 1 . adg5433 tssop and lfcsp_vq i n 1 i n 2 i n 3 i n 4 s1 a d 1 s1 b s2 b d 2 s2 a s4 a d 4 s4 b s3 b d 3 s3 a l ogi c ad g 543 4 sw i t ch es sh o w n f o r a l ogi c 1 i n pu t . 09207-002 figure 2 . adg5434 tssop general description the adg5433 and adg5434 are monolithic indust rial cmos analog switches comprising three independently selectable single - pole, double - throw (spdt) switches and four indepen - dently select able spdt switches, respectively. all channels exhibit break - before - make switching action that prevents momentary shorting when switching channels. an en input on the adg5433 (lfcsp and tssop package s) is used to enable or disable the de vice. when disabled, all channels are switched off. the ultralow on resistance and on - resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. product highlight s 1. trenc h isolation guards against latch - up. a dielectric trench separates the p and n channel transistors thereby preventing latch - up even under severe overvoltage conditions. 2. low r on . 3. dual - supply operation. for applications where the analog signal is bip olar, the adg54 33 /adg54 34 can be operated from dual supplies up to 22 v. 4. single - supply operation. for applications where the analog signal is unipolar, the adg54 33 /adg54 34 can be operated from a single - rail power supply up to 4 0 v. 5. 3 v logic compatible d igital inputs: v i n h = 2.0 v, v i n l = 0.8 v. 6. no v l logic power supply required.
adg5433/adg5434 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous current per channel, sx or dx ..............................8 absolute maximum ratings ............................................................9 esd ca ution ...................................................................................9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 12 test circuits ..................................................................................... 16 terminology .................................................................................... 18 trench isolation .............................................................................. 19 applications information .............................................................. 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 revisio n history 10 /10 revision 0: initial version
adg5433/adg5434 rev. 0 | page 3 of 24 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/co mments analog switch analog signal range v dd to v ss v on resistance, r on 13.5 ? typ v s = 10 v, i s = ?10 ma; see figure 26 15 18 22 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels, ?r on 0.3 ? typ v s = 10 v , i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 1.8 ? typ v s = 10 v, i s = ?10 ma 2 .2 2.6 3 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.05 na typ v s = 10 v, v d = ? 10 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0. 1 na typ v s = 10 v, v d = ? 10 v; see figure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 10 v; see figure 25 0.4 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input curren t, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 transition time, t trans ition 157 ns typ r l = 300 ?, c l = 35 pf 207 245 272 ns max v s = 10 v t on ( en ) 160 ns typ r l = 300 ?, c l = 35 pf 196 241 274 ns max v s = 10 v; see figure 34 t off ( en ) 91 ns typ r l = 300 ?, c l = 35 pf 106 138 140 ns max v s = 10 v; see fi gure 34 break - before - make time delay, t d 45 ns typ r l = 300 ?, c l = 35 pf 21 ns min v s1 = v s2 = 10 v; see figure 33 charge injection, q inj 130 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see fig ure 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1 m hz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; figure 27 total harmonic distortion + noise 0.01 % typ r l = 1 k ?, 15 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth 145 mhz typ r l = 50 ?, c l = 5 pf; see figure 31 insertion loss ?0.9 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 14 pf typ v s = 0 v, f = 1 mhz c d (off ) 24 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 53 pf typ v s = 0 v, f = 1 mhz
adg5433/adg5434 rev. 0 | page 4 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/co mments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a t yp digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9 /2 2 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 12.5 ? typ v s = 15 v, i s = ?10 ma; see figu re 26 14 17 21 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ? r on 0.3 ? typ v s = 15 v , i s = ?1 0 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 2.3 ? typ v s = 15 v, i s = ?10 ma 2.7 3.1 3.5 ? max leak age currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.05 na typ v s = 15 v, v d = ? 15 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0. 1 na typ v s = 15 v, v d = ? 15 v; see figure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 15 v; see figure 25 0.4 4 30 na max digital inputs in put high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 transition time, t t rans ition 150 ns typ r l = 300 ?, c l = 35 pf 199 230 253 ns max v s = 10 v t on ( en ) 152 ns typ r l = 300 ?, c l = 35 pf 186 223 253 ns max v s = 10 v; see figure 34 t off ( en ) 90 ns t yp r l = 300 ?, c l = 35 pf 104 118 130 ns max v s = 10 v; see figure 34 break - before - make time delay, t d 36 ns typ r l = 300 ?, c l = 35 pf 17 ns min v s1 = v s2 = 10 v; see figure 33 charge inj ection, q inj 176 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1mhz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27
adg5433/adg5434 rev. 0 | page 5 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments total harmonic distortion + noise 0.012 % typ r l = 1 k ?, 20 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth 140 mhz typ r l = 50 ?, c l = 5 pf; see figure 31 insertion loss ?0.8 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 15 pf typ v s = 0 v, f = 1 mhz c d (off ) 23 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 52 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd v dd /v ss 9 /2 2 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v s ingle supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resista nce, r on 26 ? typ v s = 0 v to 10 v, i s = ?10 ma; see figure 26 30 36 42 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 0.3 ? typ v s = 0 v to 10 v, i s = ?10 ma 1 1.5 1.6 ? max on - resistanc e flatness, r flat (on) 5.5 ? typ v s = 0 v to 10 v, i s = ?10 ma 6.5 8 12 ? max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.05 na typ v s = 1 v/10 v, v d = 10 v/ 1 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0. 1 na typ v s = 1 v/10 v, v d = 10 v/ 1 v; see figure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v/10 v; see figure 25 0.4 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ dynamic characteristics 1 transition time, t trans ition 220 ns typ r l = 300 ?, c l = 35 pf 290 357 400 ns max v s = 8 v t on ( en ) 228 ns typ r l = 300 ? , c l = 35 pf 289 370 426 ns max v s = 8 v; see figure 34 t off ( en ) 90 ns typ r l = 300 ? , c l = 35 pf 115 131 151 ns max v s = 8 v; see figure 34 break - before - make time delay, t d 106 ns typ r l = 300 ? , c l = 35 pf 54 ns min v s1 = v s2 = 8 v; see figure 33
adg5433/adg5434 rev. 0 | page 6 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments charge injection, q inj 60 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf; see figure 35 off isolation ? 60 db typ r l = 50 ?, c l = 5 pf, f = 1 m hz; see figure 28 channel - to - channel crosstalk ? 60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.1 % typ r l = 1 k ?, 6 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth 150 mhz typ r l = 50 ? , c l = 5 pf; see figure 31 insertion loss ?0.8 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 18 pf typ v s = 6 v, f = 1 mh z c d (off ) 28 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 54 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v sing le supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 14.5 ? typ v s = 0 v to 30 v, i s = ?10 ma; see figure 26 16 19 23 ? max v dd = 32.4 v, v ss = 0 v on - resistance match between channels, ? r on 0.3 ? typ v s = 0 v to 30 v, i s = ?10 ma 0.8 1.3 1.4 ? max on - resistance flatness, r flat (on) 3.5 ? typ v s = 0 v to 30 v, i s = ?10 ma 4.3 5.5 6.5 ? max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off ) 0.05 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 29 0.25 1 7 na max drain off leakage, i d (off ) 0. 1 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 29 0. 4 4 30 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v/30 v; see figure 25 0.4 4 30 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 6 pf typ
adg5433/adg5434 rev. 0 | page 7 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments dynamic characteristics 1 transition time, t trans ition 180 ns typ r l = 300 ?, c l = 35 pf 262 274 2 89 ns max v s = 18 v t on ( en ) 176 ns typ r l = 300 ? , c l = 35 pf 216 238 268 ns max v s = 18 v; see figure 34 t off ( en ) 98 ns typ r l = 300 ? , c l = 35 pf 123 127 129 ns max v s = 18 v; see figure 34 break - before - make time delay, t d 50 ns typ r l = 300 ? , c l = 35 pf 21 ns min v s1 = v s2 = 18 v; see figure 33 charge injection, q inj 150 pc typ v s = 18 v, r s = 0 ? , c l = 1 n f; see figure 35 off isolation ?60 db typ r l = 50 ?, c l = 5 pf, f = 1 m hz; see figure 28 channel - to - channel crosstalk ?60 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 27 total harmonic distortion + noise 0.4 % typ r l = 1 k ?, 18 v p - p, f = 20 hz to 20 khz; see figure 30 ?3 db bandwidth 135 mhz typ r l = 50 ? , c l = 5 pf; see figure 31 insertion loss ?1 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 c s (off ) 18 pf typ v s = 18 v, f = 1 mhz c d (off ) 28 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 46 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
adg5433/adg5434 rev. 0 | page 8 of 24 continuous current p er channel, s x or d x table 5 . adg5433 parameter 25c 85c 125c unit continuous current , s x or d x v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 80 58 36 ma maximum lfcsp ( ja = 30.4 c/w) 1 47 103 70 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 85 63 39 ma maximum lfcsp ( ja = 30.4 c/w) 156 109 74 ma maximum v dd = 12 v, v ss = 0 v tss op ( ja = 112.6c/w) 63 45 28 ma maximum lfcsp ( ja = 30.4 c/w) 116 84 53 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 83 60 37 ma maximum lfcsp ( ja = 30.4 c/w) 1 51 107 72 ma maximum table 6 . adg5434 parameter 25c 85c 125c unit continuous current, s x or d x v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 70 51 31 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 74 54 33 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 54 39 23 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 73 53 32 ma maximum
adg5433/adg5434 rev. 0 | page 9 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 7 . parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v s s to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or dx pins adg5433 2 8 0 ma (pulsed at 1 ms, 10% duty cycle maximum) adg5434 2 4 0 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s x or d x 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 16- lead tssop (4 - layer board) 112.6c/w 20- lead tssop (4 - layer board) 143c/w 16- lead lfcsp (4 - layer board) 30.4 c/w reflow soldering peak temperature, pb free 260(+0/ ?5)c 1 overvoltages at the inx, sx, and dx pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at thes e or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be appl ied at any one time. esd caution
adg5433/adg5434 rev. 0 | page 10 of 24 pin configurations a nd function descript ions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 s1a d1 s1b s2a d2 s2b v dd in1 en v ss s3a in2 in3 d3 s3b gnd adg5433 top view (not to scale) 09207-003 figure 3. adg5433 tssop pin configuration pin 1 indicator 1 d1 2 s1b 3 s2b 4 d2 11 v ss 12 en 10 s3b 9 d3 5 s2a 6 in2 7 in3 8 s3a 15 v dd 16 s1a 14 gnd 13 in1 top view (not to scale) adg5433 notes 1. exposed pad is tied to substrate, v ss . 09207-005 figure 4. adg5433 lfcsp_vq pin configuration table 8 . adg5433 pin function descriptions pin n o. nemonic description tssop lfcspv 1 15 v dd most positive power supply potential. 2 16 s1a source terminal 1a. this pin c an be an input or an output. 3 1 d1 drain terminal 1. this pin c an be a n input or an output. 4 2 s1b source terminal 1b. this pin c an be an input or an output. 5 3 s2b source terminal 2b. this pin c an be an input or an output. 6 4 d2 drain terminal 2. this pin c an be an input or an output. 7 5 s2a source terminal 2a. this pin c an be an input or an output. 8 6 in2 logic control input 2 . 9 7 in3 logic control input 3 . 10 8 s3a source terminal 3a. this pin c an be an input or an output. 11 9 d3 drain terminal 3. this pin c an be an input or an output. 12 10 s3b source term inal 3b. this pin c n be an input or an output. 13 11 v ss most negative po wer supply potential. in single - supply applicatio ns, this pin c an be connected to ground. 14 12 en active low digital input. when high, the device is disa bled and all switches are off. when low, inx logic inputs determine the on switches. 15 13 in1 logic control input 1 . 16 14 gnd ground (0 v) reference. ep exposed pad the exposed pad is connected internally. for increased reliability of the solder joints and ma ximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . table 9 . adg5433 truth table en in sa s b 1 x off off 0 0 off on 0 1 on off
adg5433/adg5434 rev. 0 | page 11 of 24 1 2 3 4 5 6 8 20 19 18 17 16 15 13 s1a d1 s1b 7 s2b gnd v ss in1 s4a d4 s4b 14 s3b 9 s2a 12 s3a 10 in2 11 in3 d2 d3 nc v dd in4 adg5434 top view (not to scale) nc = no connect 09207-004 figure 5 . adg5434 tssop pin configuration table 10. adg5434 pin function descriptions pin no. mnemonic description 1 in1 logic control input 1. 2 s1a source terminal 1a. this pin c an be an input or an output. 3 d1 drain terminal 1. th is pin c an be an input or an output. 4 s1b source terminal 1b. this pin c an be an input or an output. 5 v ss most negative power supply potential. in single - supply applications, this pin c an be connected to ground. 6 gnd ground (0 v) reference. 7 s2b so urce terminal 2b. this pin c an be an input or an output. 8 d2 drain terminal 2. this pin c an be an input or an output. 9 s2a source terminal 2a. this pin c an be an input or an output. 10 in2 logic control input 2. 11 in3 logic control input 3. 12 s3a source terminal 3a. this pin c an be an input or an output. 13 d3 drain terminal 3. this pin c an be an input or an output. 14 s3b source terminal 3b. this pin c an be an input or an output. 15 nc no connect. 16 v dd most positive power supply potential. 17 s4b source terminal 4b. this pin c an be an input or an output. 18 d4 drain terminal 4. this pin c an be an input or an output. 19 s4a source terminal 4a. this pin c an be an input or an output. 20 in4 logic control input 4. table 11. adg5434 truth table inx sxa sxb 0 off on 1 on off
adg5433/adg5434 rev. 0 | page 12 of 24 typical performance characteristics 0 5 10 15 20 25 ?18 ?14 ?10 ?6 ?2 2 6 10 14 18 on resis t ance () v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +10v v ss = ?10v v dd = +11v v ss = ?11v v dd = +13.5v v ss = ?13.5v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09207-047 figure 6 . on resistance as a function of v s , v d ( dual supply ) 0 2 4 6 8 10 12 14 16 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resis t ance () v s , v d (v) t a = 25c v dd = +22v v ss = ?22v v dd = +20v v ss = ?20v v dd = +18v v ss = ?18v 09207-048 figure 7. on resistance as a funct ion of v s , v d ( dual supply ) 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 on resis t ance () v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10v v ss = 0v v dd = 10.8v v ss = 0v v dd = 11v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09207-044 figure 8. on resistance as a function of v s , v d (single supply ) 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 45 on resis t ance () v s , v d (v) t a = 25c v dd = 39.6v v ss = 0v v dd = 36v v ss = 0v v dd = 32.4v v ss = 0v 09207-046 figure 9. on resistance as a function of v s , v d (single supply) 0 5 10 15 20 25 ?15 ?10 ?5 0 5 10 15 on resis t ance () v s , v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09207-049 figure 10 . o n resistance as a function of v s (v d ) for different temperatures, 15 v dual supply 0 5 10 15 20 25 ?20 ?15 ?10 ?5 0 5 10 15 20 on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v s , v d (v) v dd = +20v v ss = ?20v 09207-045 figure 11 . on resistance as a function of v s (v d ) for different temperatures, 20 v dual supply
adg5433/adg5434 rev. 0 | page 13 of 24 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 v s , v d (v) on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v 09207-050 figure 12 . on resi stance as a function of v s (v d ) for different temperatures, 12 v single supply 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 on resis t ance () t a = +125c t a = +85c t a = +25c t a = ?40c v s , v d (v) v dd = 36v v ss = 0v 09207-051 figure 13 . on resistance as a function of v s (v d ) for different temperatures, 36 v single supply 0 25 50 75 100 125 leakage current (na) temper a ture (c) 0.6 0.4 ?0.2 0 ?0.4 0.2 v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09207-041 figure 14 . leakage cur rents as a function of temperature, 15 v dual supply 0 25 50 75 100 125 leakage current (na) temper a ture (c) 0.4 0.2 ?0.2 0 ?0.4 ?0.6 v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i s (off) + ? i d (off) + ? i s (off) ? + i d , i s (on) ? ? i d (off) ? + 09207-042 figure 15 . leakage currents as a function of temperature, 20 v dual supply 0 25 50 75 100 125 leakage current (na) temper a tur e (c) 0.4 0.3 ?0.2 0 ?0.1 0.2 0.1 v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09207-040 figure 16 . leakage currents as a function of temperature, 12 v sin gle supply leakage current (na) temper a tur e (c) 0 25 50 75 100 125 0.4 0.2 ?0.2 0 ?0.4 ?0.6 v dd = 36v v ss = 0v v bias = 1v/30v i d , i s (on) + + i s (off) + ? i d (off) + ? i s (off) ? + i d , i s (on) ? ? i d (off) ? + 09207-043 figure 17 . leakage currents as a function of temperature, 36 v single supply
adg5433/adg5434 rev. 0 | page 14 of 24 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 1k 10k 100k 1m 10m 100m 1g off isolation (db) frequency (hz) 09207-036 t a = 25c v dd = +15v v ss = ?15v figure 18 . off isolation vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m 10m 100m 1g crosstalk (db) frequency (hz) 09207-039 t a = 25c v dd = +15v v ss = ?15v figure 19 . crosstalk vs. frequency 350 0 ?20 40 charge injection (pc) v s (v) 09207-033 50 100 150 200 250 300 10 0 10 20 30 t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v figure 20 . charge injection vs. source voltage 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 1k 10k 100k 1m 10m acpsrr (db) frequency (hz) 09207-037 no decoupling capacitors decoupling capacitors t a = 25c v dd = +15v v ss = ?15v figure 21 . acpsrr vs. frequency 0.12 0.10 0.08 0.06 0.04 0.02 0 0 20k 15k 10k 5k thd + n (%) frequency (hz) 09207-038 load = 1k ? t a = 25c v dd = 12v, v ss = 0v, v s = 6v p-p v dd = 36v, v ss = 0v, v s = 18v p-p v dd = 15v, v ss = 15v, v s = 15v p-p v dd = 20v, v ss = 20v, v s = 20v p-p figure 22 . thd + n vs. frequency 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 1k 10k 100k 1m 10m 100m 1g insertion loss (db) frequency (hz) 09207-035 t a = 25c v dd = +15v v ss = ?15v figure 23 . bandwidth
adg5433/adg5434 rev. 0 | page 15 of 24 350 0 ?40 120 time (ns) temperature (c) 09207-034 50 100 150 200 250 300 ?200 20406080100 v dd = +12v, v ss = 0v v dd = +36v, v ss = 0v v dd = +15v, v ss = ?15v v dd = +20v, v ss = ?20v figure 24. t transition times vs. temperature
adg5433/adg5434 rev. 0 | page 16 of 24 test circuits sx dx a v d i d (on) nc nc = no connect 09207-023 figure 25 . on leakage i ds sx dx v s v 09207-021 figure 26 . on resistance channel-to-channel crosstalk = 20 log v out gnd sxa dx sxb v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss inx 09207-030 figure 27 . channe l - to - channel crosstalk v out 50? network analyzer r l 50? in v in sxa dx v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sxb off isolation = 20 log v out v s 09207-028 figure 28 . off isolation sx dx v s a a v d i s (off) i d (off) 09207-022 figure 29 . off leakage v out r s audio precision r l 1k? inx v in sx dx v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 09207-031 figure 30 . thd + noise v out 50? network analyzer r l 50? inx v in sxa dx v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sxb insertion loss = 20 log v out with switch v out without switch 09207-029 figure 31 . bandwidth
adg5433/adg5434 rev. 0 | page 17 of 24 inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300? 50% 50% 90% 50% 50% 90% t on t off v in v out v in 09207-024 figure 32 . switching timing i n x v o u t d x sxa v d d v s s v d d v s s g n d c l 3 5 p f sx b v i n v s 0 . 1 f 0 . 1 f r l 30 0 ? 8 0 % t d t d v o u t v i n 09207-025 figure 33 . break - before - make delay, t d en in2 v dd v ss v dd v ss gnd adg5433 in1 s1b s1a v in 0.1f 0.1f in3 v s v out d1 c l 35pf 50% 0.9v out 0.9v out t on (en) 50% v out 0v 0v enable drive (v in ) output 3v t off (en) r l 300? 50? 09207-026 figure 34 . enable delay, t on ( en ), t off ( en ) v i n (n o r ma lly c l o sed sw i t ch ) v o u t v i n (n o r ma lly o pen sw i t ch ) o f f v o u t o n q i n j = c l v o u t i nx v o u t n c sx a v d d v s s v d d v s s g n d c l 1 n f d x v i n v s 0 . 1 f 0 . 1 f sx b 09207-027 figure 35 . charge injection
adg5433/adg5434 rev. 0 | page 18 of 24 terminology i dd i dd represents the p ositive supply current. i ss i ss represents the n egative supply current. v d , v s v d and v s represent t he analog voltage on terminal d and terminal s , respectively . r on r on is the o hmic resistance between terminal d and terminal s. ? r on ? r on represents t he d ifference between the r on of any two channels . r flat (on) the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacit ance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in represents digital input capacitance. t on ( en t on ( ) en t off ( ) represents the d elay time between the 50% and 90% points of the digital input and switch on condition. en t off ( ) en t trans ition ) represents the d elay time between the 50% and 90% points of the digital input and switch off condition. delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t d t d represents the o ff time measured between the 80% point of both sw itches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off channel. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a res ult of parasitic capacitance. bandwidth bandwidth is t he frequency at which the output is attenuated by 3 db. on response on response is t he frequency response of the on switch. t otal h armonic d istortion + n oise (thd + n) the ratio of the harmonic amplitud e plus noise of the signal to the fundamental is represented by thd + n . ac power supply rejection ratio (acpsrr) acpsrr is a measure of the ability of a part to avoid coupling noise and spurious signals that ap pear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p - p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsr r.
adg5433/adg5434 rev. 0 | page 19 of 24 trench isolation in the adg54 33/adg5434, an insulating oxide lay er (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch - up proof switch. in junction i solation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltage conditions, this diode can become forward - biased. a silicon controlled rectifier (scr) type circuit is form ed by the two transistors causing a significant amplification of the current that , in turn, leads to latch - up. with trench isolation, this diode is removed, and the result is a latch - up proof switch. 09207-032 nmos pmos p- w e l l n - w e l l buried oxide layer handle wafer t r e n c h figure 36 . trench isolation
adg5433/adg5434 rev. 0 | page 20 of 24 applications informa tion the adg54xx family of switches and multiplexers provide a robust solution for instrumentation, i ndustrial, automotive , aero - space and other harsh environments that are prone to latch - up, which is an undesirable high current stat e that can lead to device failure and persist s until t he power supply is turned off. the adg5433/adg5434 high voltage switches allow single - supply operation from 9 v to 40 v and dual supply operation from 9 v to 22 v. the adg54 3 3 / adg5434 (as well as othe r select devices within this family ) achieve 8 kv human body model esd rating s, which provide a robust solution eliminating the need for separate protect circuitry designs in some applications.
adg5433/adg5434 rev. 0 | page 21 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 37 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 012909-b 1 0.65 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 38 . 16 - lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very very thin quad (cp - 16 - 17) dimensions shown in millimeters
adg5433/adg5434 rev. 0 | page 22 of 24 compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 39 . 20 - lead thin shrink small outline package [tssop] (ru - 20) dimensions shown in millimeters ordering guide model 1 temperature range description en p in package option adg5433bruz ?40c to +125c 16-l ead thin shrink small outline package [ tssop ] yes ru -16 adg5433bruz - reel7 ?40c to +125c 16- lead thin shrink small outline package [ tssop ] yes ru -16 adg5433bcpz - reel7 ?40c to +125c 16- lead lead frame chip scale package [ lfcsp_vq ] yes cp -16-17 adg5 434 b ruz ?40 c to +125 c 20- lead thin shrink small outline package [tssop] no ru -20 adg5434 b ruz - reel7 ?40 c to +125 c 20- lead thin shrink small outline package [tssop] no ru -20 1 z = rohs compliant part.
adg5433/adg5434 rev. 0 | page 23 of 24 notes
adg5433/adg5434 rev. 0 | page 24 of 24 notes ? 2010 analog dev ices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09207 - 0- 10/10(0)

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